One-chip semiconductor device with voltage stop

专利摘要:
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip semiconductor device having a voltage rectifying device. In particular, the present invention relates to a bias driver which generates a bias current by receiving a power supply voltage VDD in response to a drive signal, and a reference voltage by a current flowing from the bias driver. A reference voltage generator for generating a voltage, a comparison voltage generator for generating a comparison voltage by the current flowing from the driver, and a differential amplifier for comparing the respective voltages of the reference voltage generator and the comparison voltage generator and outputting a difference thereof. And a ground potential of the power supply voltage threshold having a reference voltage controller for sensing the output signal of the differential amplifier and adjusting the amount of current to the substrate bias potential VBB.
公开号:KR19990030995A
申请号:KR1019970051509
申请日:1997-10-08
公开日:1999-05-06
发明作者:유승빈
申请人:윤종용；삼성전자 주식회사；
IPC主号:

专利说明:

One-chip semiconductor device with voltage stop
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip semiconductor device having a voltage rectifying device, and more particularly, to a one-chip semiconductor device having a voltage rectifying device capable of improving the reliability of an image semiconductor device requiring high resolution.
Typically the voltage stop serves to provide a constant direct current voltage to the circuit system. The voltage stop value should not change the output voltage according to the state of the voltage output stage, that is, the load, and must maintain a constant DC voltage against the fluctuation of the power supply. Accordingly, many studies and developments of power supply rejection ratios (PSRRs), for example, to reduce the impact on power supply fluctuations, are under way to improve load rectification.
However, in the case of a one-chip semiconductor device having a voltage stop value, the voltage stop value inevitably affects the voltage stop value because many transistors are connected to the power supply voltage and the source voltage terminal. In addition, digital circuits using clock signals suffer more damage, so analog and digital circuits are generally designed to have separate power supplies. However, even in this design, since the semiconductor device has various signals mixed in the analog power line itself, the semiconductor device is smaller than the clocking noise of the power supply for the digital circuit, but still adversely affects the voltage stop.
SUMMARY OF THE INVENTION An object of the present invention is to provide a one-chip semiconductor device having a voltage stop that can improve the PSRR by connecting the source potential of the voltage stop from analog ground to the substrate potential in order to solve the problems of the prior art. .
In order to achieve the above object, the device of the present invention is a one-chip semiconductor device having a voltage stop for converting an AC signal into a direct current signal, wherein the ground potential of the transistor constituting the voltage stop is connected to the substrate bias. do.
1 is a circuit diagram showing an embodiment of a voltage stop according to the present invention.
2 is a vertical sectional view of an NMOS transistor constituting a voltage stop value according to the prior art.
3 is a vertical sectional view of an NMOS transistor constituting the voltage stop shown in FIG.
* Description of the symbols for the main parts of the drawings *
2: P-type substrate 4: gate
5, 6: Drain / Source 7: P-type impurity region
10: bias driver 20: reference voltage generator
30: comparison voltage generator 40: differential amplifier
50: current mirror 60: reference voltage control
Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
1 is a circuit diagram illustrating an embodiment of a voltage stop according to the present invention, in which the first and seventh PMOS transistors MP0 to drain connected to a power supply voltage VDD terminal and a gate connected to a word line. A first bipolar transistor Q1 having an emitter connected to a bias driver 10 having MP6 and a source of a third PMOS transistor MP2 of the bias driver 10 and a collector connected to a substrate potential VBB terminal. ), A second bipolar transistor Q3 having a resistor R4 connected to the source of the fourth PMOS transistor MP3 and an emitter connected to the resistor R4, and a base and a collector connected to a substrate potential VBB terminal. An emitter is connected to a reference voltage generator 20 having a voltage, a resistor R2 connected to a source of the second PMOS transistor MP1 of the bias driver 10, and an emitter connected to the resistor R2, and a collector is connected to a substrate potential. To the (VBB) terminal The emitter is connected to a node of the third bipolar transistor Q0, the resistor R3 connected to the source of the first PMOS transistor MP0, and the base of the resistor R3 and the third bipolar transistor Q0. A comparison voltage generator 30 having a fourth bipolar transistor Q2 connected to the substrate potential VBB terminal and having a collector and a base connected in common, and a source of the fifth PMOS transistor MP4 of the bias driver 10. And an eighth PMOS transistor having a common drain connected to each other and having a gate connected to a source node of the third PMOS transistor MP2 of the reference voltage generator 20 and an emitter of the first bipolar transistor Q1. A differential amplifier 40 having a ninth PMOS transistor MP8 having a gate connected to the source of the second PMOS transistor MP1 of the comparison voltage generator 30 and the connection node of the resistor R2. ) And the differential increase First and second drains are respectively connected to the sources of the eighth PMOS transistor MP7 and the ninth PMOS transistor MP8 of the unit 40, the substrate potential VBB terminal is connected to the source, and the base is commonly connected. The emitter is connected to the current mirror 50 having the NMOS transistors MN0 to MN1, a resistor R0 connected to a source of the seventh PMOS transistor MP6 of the bias driver 10, and the resistor R0. The drain is connected to a node connected to a source of the fifth bipolar transistor Q4, a source of the sixth PMOS transistor MP5, and a base of the fifth bipolar transistor Q4 connected to a collector and connected to a substrate potential VBB terminal. The third NMOS transistor MN2 connected to the substrate potential VBB terminal, the capacitor C and the resistor R1 connected in series between the source of the sixth PMOS transistor MP5 and the substrate potential VBB terminal are connected. The branch is constituted by the reference voltage controller 60.
The voltage rectifying device according to the present invention configured as described above is mainly used as a reference voltage generating circuit of an analog circuit because there is almost no voltage change with temperature at about 300K at room temperature by using a band-gap reference circuit. . In the band-gap reference circuit of the present invention, when the bias current flows through the power supply voltage VDD through the bias driver 10, the reference voltage generator 20 and the comparison voltage generator 30 are compared with the reference voltage. Respectively, and the differential amplifier 40 compares these voltages, and turns on the third NMOS transistor MN2 of the reference voltage controller 60 according to the voltage difference to discharge the charged voltage stored in the capacitor. do. Accordingly, the output voltage vbgr, which is a reference voltage of the band-gap reference, is a constant voltage, and more specifically, the threshold voltage and the threshold between the base emitters of the fifth bipolar transistor Q4 by the amount of current flowing during the discharge time of the charging voltage. Output the voltage as the sum of voltages.
On the other hand, in recent years, analog and digital mixing systems requiring high resolution are applying the substrate bias of the MOS transistor to the ground potential separately from the source potential (VSS) in order to prevent the clocking noise of the digital block from being input through the silicon substrate. In accordance with this trend, the present invention connects the ground potential of the elements constituting the band-gap reference circuit to the substrate potential (VBB) terminal. Accordingly, since the band-gap reference generates a DC voltage only by the power supply voltage VDD, changing the source potential of the MOS transistor among the devices does not affect the substrate noise. As a result, the band-gap reference circuit can always supply a stable output voltage by the substrate potential VBB even if the ground potential VSS is changed by the influence of another circuit.
2 is a vertical cross-sectional view of an NMOS transistor constituting a voltage stop according to the prior art, wherein the NMOS transistor is formed on the P-type substrate 2 and has a gate 4 connected to a word line W / L, N + impurity is implanted at a high concentration into the P-type substrate 2 near the edge of the gate 4 and is composed of drains / sources 5 and 6 connected to the bit line B / L and the source potential VSS, respectively.
FIG. 3 is a vertical cross-sectional view of the NMOS transistor constituting the voltage stop shown in FIG. 1, wherein the NMOS transistor is formed on the P-type substrate 2 and is connected to the word line W / L. In the P-type substrate 2 near the edge of the gate 4, a high concentration of N + impurities are injected, and the drain / source 5 and 6 are respectively connected to the bit line B / L and the substrate potential VBB. .
2 to 3, in the conventional NMOS transistor, only a P-type impurity region 7 in which P-type impurities are injected into the P-type substrate 2 at a high distance from the source 6 is implanted. It is connected to the potential VBB. As a result, conventional NMOS transistors are electrically mutually affected by a common ground whose source is connected to the NMOS transistor source of another circuit. On the other hand, in the NMOS transistor according to the present invention, the P-type impurity region 7 and the source 6 are connected to the substrate potential VBB together. As a result, the NMOS transistor of the present invention prevents the electrical mutual influence due to the common ground with other circuits since the sources are all connected to the substrate potential.
Since the present invention connects the ground potential of the voltage stop to the substrate, the stable output voltage can be supplied even if the ground potential is changed by another circuit, thereby improving the problem of PSRR due to the ground voltage.

权利要求:
Claims (2)
[1" claim-type="Currently amended] In a one-chip semiconductor device having a voltage stop for converting an AC signal into a DC signal,
A one-chip semiconductor device having a voltage stop value, wherein the ground potential of the voltage stop value is connected to a substrate bias.
[2" claim-type="Currently amended] The one-chip semiconductor device according to claim 1, wherein the voltage stop value connects a source potential of a MOS transistor to a substrate bias.

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同族专利:

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1997-10-08|Application filed by 윤종용, 삼성전자 주식회사

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1997-10-08|Priority to KR1019970051509A

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1999-05-06|Publication of KR19990030995A

优先权:

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申请号 | 申请日 | 专利标题

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KR1019970051509A|KR19990030995A|1997-10-08|1997-10-08|One-chip semiconductor device with voltage stop|